Conventional method to form STI (Shallow Trench Isolation) structure is shown in FIGS. 1A, 1B, and 1C. In FIG. 1A, a pad oxide layer 11 and a silicon nitride layer 12 are sequentially formed on a substrate 10. Next, a photoresist layer 14 with a trench pattern is formed on the silicon nitride layer 12 by a photolithography process. Then a trench 16 is formed by performing an anisotropic etching on the substrate 10 according to the trench pattern on the photoresist layer 14.
In FIG. 1B, after removing the photoresist layer 14, a thermal oxide layer 18 is formed on the trench surface by thermal oxidation at 20 a temperature of about 900.degree. C..about.1100.degree. C. An oxide layer 20 is formed over the substrate 10 by atmospheric chemical vapor deposition (APCVD) with a reaction gas of tetra-ethyl-ortho-silicate (TEOS).
In FIG. 1C, a chemical mechanical polishing (CMP) process is performed to polish the TEOS oxide layer 20 above the silicon nitride 12. The remained TEOS oxide layer filled in the trench 16 is called an oxide plug 20a and is used for isolation. However, the CMP process will cause a dishing-type surface to be formed on the surface of the oxide plug 20a when the trench is wide, as shown in the figure.
In U.S. Pat. No. 6,110,800 Chou disclosed a method to form a shallow trench isolation (STI) structure. FIGS. 2A.about.2G show schematically the Chou's process in forming a STI structure by repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers.
In FIG. 2A, a photoresist 202 is formed over a semiconductor substrate 200. A photolithography process is performed to transfer a pattern onto the substrate 200. Then an anisotropic etching is performed to form a trench 204 and a trench 206 on the substrate. The trench 204 is wider than the trench 206.
In FIG. 2B, an ion implantation is performed to form a channel stop 205 under the trench 204, 206, and then the photoresist layer 202 is removed. A pad oxide layer 208 and a silicon nitride 210 are sequentially formed over the substrate 200.
In FIG. 2C, a polysilicon layer is deposited over the substrate 200 through LPCVD and performing an etching back process to form a sidewall spacer 212b and a sidewall spacer 212a respectively on each side of the trench 204 and the trench 206 over the silicon nitride layer 210.
In FIG. 2D, an oxidation process is performed to oxidize the sidewall spacers 212a, 212b. Since the trench 206 is narrow, an oxide plug 214a is formed to fill the trench 206. The trench 204 is wide, an oxide sidewall aspacer 214b may be formed without filling the trench 204. In order to fully fill the trench 204 with oxide, another polysilicon sidewall spacer 216 is repeatedly formed and oxidized until an oxide plug 218 is formed to fully fill the trench 204 as shown in FIG. 2E.
In FIG. 2F, an oxide layer 220 is formed over the substrate 200 to have a better planar surface.
In FIG. 2G, an anisotropic etching process is performed to remove the oxide layer 220, the silicon nitride layer 210, and the pad oxide layer 208 outside the trenches 204, 206 to expose the substrate 200.
The Chou's method needs repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers. Though this process can somewhat eliminate the dishing-effect in a wider trench, it is too complicated and costly.